information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg752 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: ? analog devices, inc., functional block diagram cmos, low voltage rf/ video, spdt switch in d s2 s1 adg752 switch shown for a logic "1" input features high off isolation C80 db at 30 mhz C3 db signal bandwidth 250 mhz +1.8 v to +5.5 v single supply low on-resistance (15 v typically) low on-resistance flatness fast switching times t on typically 8 ns t off typically 3 ns typical power consumption < 0.01 m w ttl/cmos compatible applications audio and video switching rf switching networking applications battery powered systems communication systems relay replacement sample-and-hold systems general description the adg752 is a low voltage spdt (single pole, double throw) switch. it is constructed using switches in a t-switch configura- tion, which results in excellent off isolation while maintaining good frequency response in the on condition. high off isolation and wide signal bandwidth make this part suitable for switching rf and video signals. low power con- sumption and operating supply range of +1.8 v to +5.5 v make it ideal for battery powered, portable instruments. the adg752 is designed on a submicron process that provides low power dissipation yet gives high switching speed and low on resistance. this part is a fully bidirectional switch and can handle signals up to and including the supply rails. break-before-make switching action ensures the input signals are protected against momentary shorting when switching between channels. the adg752 is available in 6-lead sot-23 and 8-lead m soic packages. product highlights 1. high off isolation C80 db at 30 mhz. 2. C3 db signal bandwidth 250 mhz. 3. low on resistance (15 w ). 4. low power consumption, typically <0.01 m w. 5. break-before-make switching action. 6. tiny 6-lead sot-23 and 8-lead m soic packages. 2013 781/461-3113 rev. a
C2C adg752Cspecifications (v dd = +5 v 6 10%, gnd = 0 v, unless otherwise noted.) b version C40 8 c parameter +25 8 c to +85 8 c units test conditions/comments analog switch analog signal range 0 v to v dd v on-resistance (r on )1 5 w typ v s = 0 v to v dd , i ds = 10 ma; 18 20 w max test circuit 1 on-resistance match between 0.1 w typ v s = 0 v to v dd , i ds = 10 ma channels ( d r on ) 0.6 0.6 w max on-resistance flatness (r flat(on) )2 w typ v s = 0 v to 2.5 v, i ds = 10 ma 3 w max v dd = + 4.5 v leakage currents source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.25 3.0 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v d = v s = 1 v, or 4.5 v; 0.25 3.0 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.001 m a typ v in = v inl or v inh 0.5 m a max c in , digital input capacitance 2 pf typ dynamic characteristics 1 t on 8 ns typ r l = 300 w , c l = 35 pf; 13 ns max v s = 3 v, test circuit 4 t off 3 ns typ r l = 300 w , c l = 35 pf; 5 ns max v s = 3 v, test circuit 4 break-before-make time delay 6 ns typ r l = 300 w , c l = 35 pf; 1 ns min v s = 3 v, test circuit 5 off isolation C80 db typ r l = 50 w , c l = 5 pf, f = 30 mhz; test circuit 6 crosstalk C80 db typ r l = 50 w , c l = 5 pf, f = 30 mhz; test circuit 7 C3 db bandwidth 250 mhz typ r l = 50 w , c l = 5 pf, test circuit 8 c s (off) 4 pf typ c d , c s (on) 15 pf typ power requirements v dd = +5.5 v i dd 0.001 m a typ digital inputs = 0 v or +5.5 v 0.1 0.5 m a max notes 1 guaranteed by design, not subject to production test. specifications subject to change without notice. rev. a
C3C adg752 (v dd = +3 v 6 10%, gnd = 0 v, unless otherwise noted.) b version C40 8 c parameter +25 8 c to +85 8 c units test conditions/comments analog switch analog signal range 0 v to v dd v on-resistance (r on )3 5 w typ v s = 0 v to v dd , i ds = 10 ma; 50 w max test circuit 1 on-resistance match between 0.2 w typ v s = 0 v to v dd , i ds = 10 ma channels ( d r on ) 2.5 2.5 w max leakage currents v dd = +3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.25 3.0 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v s = v d = 1 v or 3 v; 0.25 3.0 na max test circuit 3 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current i inl or i inh 0.001 m a typ v in = v inl or v inh 0.5 m a max c in , digital input capacitance 2 pf typ dynamic characteristics 1 t on 10 ns typ r l = 300 w , c l = 35 pf; 18 ns max v s = 2 v, test circuit 4 t off 4 ns typ r l = 300 w , c l = 35 pf; 8 ns max v s = 2 v, test circuit 4 break-before-make time delay 6 ns typ r l = 300 w , c l = 35 pf; 1 ns min v s = 2 v, test circuit 5 off isolation C80 db typ r l = 50 w , c l = 5 pf, f = 30 mhz; test circuit 6 crosstalk C80 db typ r l = 50 w , c l = 5 pf, f = 30 mhz; test circuit 7 C3 db bandwidth 250 mhz typ r l = 50 w , c l = 5 pf, test circuit 8 c s (off) 4 pf typ c d , c s (on) 15 pf typ power requirements v dd = +3.3 v i dd 0.001 m a typ digital inputs = 0 v or +3.3 v 0.1 0.5 m a max notes 1 guaranteed by design, not subject to production test. specifications subject to change without notice. specifications rev. a
adg752 C4C table i. truth table adg752 in switch s1 switch s2 0 on off 1 off on caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg752 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v analog, digital inputs 2 . . . . . . . . . . . . C0.3 v to v dd +0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . .100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c power dissipation . . . . . . . . . . . . . . . . . . . . . (t j maxCt a )/ q ja junction temperature (t j max) . . . . . . . . . . . . . . . . . .+150 c m soic package q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 206 c/w q jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . 44 c/w sot-23 package q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 229.6 c/w q jc thermal impedance . . . . . . . . . . . . . . . . . . . . 91.99 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. only one absolute maxi- mum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. terminology v dd most positive power supply potential. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. r on ohmic resistance between d and s. d r on on resistance match between channels, i.e., r on maxCr on min. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resis- tance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d and s. c s (off) off switch source capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. see test circuit 4. t off delay between applying the digital control input and the output switching off. t d off time or on time measured between the 90% points of both switches, when switch- ing from one address state to another. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is c oupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenu- ated by C3 dbs. on response the frequency response of the on switch. insertion loss loss due to the on resistance of the switch. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. i dd positive supply current. pin configurations 6-lead sot-23 (rt-6) 1 2 3 6 5 4 top view (not to scale) adg752 in d v dd s1 gnd s2 8-lead m soic (rm-8) 1 2 3 4 8 7 6 5 top view (not to scale) nc = no connect adg752 nc nc s1 d v dd s2 gnd in rev. a
adg752 C5C v d or v s drain source voltage C volts 35 5 01 r on C v 23 4 5 30 25 20 15 10 v dd = +5.5v t a = +25 8c v dd = +2.7v v dd = +3.3v v dd = +4.5v 40 5.5 figure 1. on resistance as a function of v d (v s ) single supplies v d or v s drain source voltage C volts 40 0 0 0.5 r on C v 1.0 1.5 2.0 2.5 35 30 25 20 15 C408c 3.0 +258c +858c v dd = +3v 10 5 figure 2. on resistance as a function of v d (v s ) for different temperatures v dd = 3 v v d or v s drain source voltage C volts 40 10 01 r on C v 23 35 30 25 20 15 5 +258c v dd = +5v 4 0 5 C408c +858c figure 3. on resistance as a function of v d (v s ) for different temperatures v dd = 5 v frequency C hz 10n 100 i dd C amps 1k 10k 100n 10m 1m 1m 10m 100k 100m 10m +5v +3v t a = +258c figure 4. supply current vs. input switching frequency frequency C mhz C120 0.1 100 off isolation C db 10 1 C100 C80 C60 C40 t a = +25c figure 5. off isolation vs. frequency frequency C mhz C80 crosstalk C db C60 C40 C20 0 0.1 1 10 100 C140 C120 C100 t a = +258c figure 6. crosstalk vs. frequency typical performance characteristicsC rev. a
adg752 C6C frequency C mhz 100 attenuation C db 10 1 C8 C4 C2 0 C6 t a = +258c figure 7. on response vs. frequency general description the adg752 is an spdt switch constructed using switches in a t configuration to obtain high off isolation while main- taining good frequency response in the on condition. figure 8 shows the t-switch configuration. while the switch is in the off state, the shunt switch is closed and the two series switches are open. the closed shunt switch provides a signal path to ground for any of the unwanted signals that find their way through the off capacitances of the series mos devices. this results in more improved isolation between the input and output than with an ordinary series switch. when the switch is in the on condition, the shunt switch is open and the signal path is through the two series switches which are now closed. d in s series shunt figure 8. basic t-switch configuration layout considerations where accurate high frequency operation is important, careful consideration should be given to the printed circuit board layout and to grounding. wire wrap boards, prototype boards and sockets are not recommended because of their high parasitic inductance and capacitance. the part should be soldered di- rectly to a printed circuit board. a ground plane should cover all unused areas of the component side of the board to provide a low impedance path to ground. removing the ground planes from the area around the part reduces stray capacitance. good decoupling is important in achieving optimum perfor- mance. v dd should be decoupled with a 0.1 m f surface mount capacitor to ground mounted as close as possible to the device itself. v dd in adg752 d s1 s2 75v v out 75v ch1 ch2 a = 2 250v 250v 75v 75v figure 9. multiplexing between two video signals rev. a
adg752 C7C v s v out 50v network analyzer r l 50v in gnd v dd v dd v in s 0.1mf d insertion loss = 20 log v out with switch v out without switch test circuit 8. bandwidth sd v s r on = v1/i ds i ds v1 test circuit 1. on resistance sd v s a v d i s (off) test circuit 2. off leakage sd a v d i d (on) nc nc = no connect test circuit 3. on leakage test circuits channel-to-channel crosstalk = 20 log gnd v dd 0.1mf v dd s1 d s2 v s v out network analyzer r l 50v in v out v s 50v test circuit 7. channel-to-channel crosstalk v s v out 50v network analyzer r l 50v in gnd v dd v dd v in s 0.1mf d 50v off isolation = 20 log v out v s test circuit 6. off isolation 50% 50% 50% 50% t d t d 0v 0v v out v in in gnd r l 300v c l 35pf v out v dd 0.1mf v dd s1 d s2 v s d2 v in test circuit 5. break-before-make time delay, t d v s in gnd r l 300v c l 35pf v out v dd 0.1mf v dd s1 d s2 90% 90% 50% 50% v in v out t off t on gnd v s test circuit 4. switching times rev. a
adg752 rev. a | page 8 outline dimensions figure 10. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters figure 11. 6-lead small outline transistor package [sot-23] (rj-6) dimensions shown in millimeters compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b compliant to jedec standards mo-178-ab 10 4 0 seating plane 1.90 bsc 0.95 bsc 0.60 bsc 65 123 4 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.20 max 0.08 min 0.50 max 0.30 min 0.55 0.45 0.35 pin 1 indicator 12-16-2008-a
adg752 rev. a | page 9 ordering guide model 1 temperature range brand package description package option adg752brm-reel ?40c to +85c seb 8-lead mini small outline package [msop] rm-8 adg752brmz ?40c to +85c s1h 8-lead mi ni small outline package [msop] rm-8 adg752brt-reel ?40c to +85c seb 6-lead small outline transistor package [sot-23] rj-6 adg752brt-reel7 ?40c to +85c seb 6-lead sma ll outline transistor package [sot-23] rj-6 adg752brtz-reel ?40c to +85c seb# 6-lead sm all outline transistor package [sot-23] rj-6 adg752brtz-reel7 ?40c to +85c seb# 6-lead sm all outline transistor package [sot-23] rj-6 1 z = rohs compliant part. revision history 10/13rev. 0 to rev. a updated outline dimensions ......................................................... 8 changes to ordering guide ............................................................ 9 4/99revision 0: initial version ?1999C2013 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d3568-0-10/13(a)
|
